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6.5 v, 4 a, high efficiency, step-down dc-to-dc regulator data sheet adp2164 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 4 a continuous output current 43 m and 29 m integrated fet 1.5% output accuracy input voltage range: 2.7 v to 6.5 v output voltage: 0.6 v to v in switching frequency fixed frequency: 600 khz or 1.2 mhz adjustable frequency: 500 khz to 1.4 mhz synchronizable from 500 khz to 1.4 mhz selectable synchronize phase shift: 0 or 180 current mode architecture precision enable input power-good output voltage tracking input integrated soft start internal compensation starts up into a precharged output uvlo, ovp, ocp, and thermal shutdown available in 16-lead, 4 mm 4 mm lfcsp package applications point-of-load conversion communications and networking equipment industrial and instrumentation consumer electronics typical applications circuit 09944-001 adp2164 pgood en c out c1 r2 r t c in v out v in sync trk rt sw fb pgnd gnd vin l r1 pvin figure 1. 100 95 90 85 80 75 70 65 60 55 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output current (a) efficiency (%) 09944-002 v in = 5v f s = 600khz v out = 1.2v v out = 3.3v figure 2. efficiency vs. output current general description the adp2164 is a 4 a, synchronous, step-down dc-to-dc regulator in a compact 4 mm 4 mm lfcsp package. the regulator uses a current mode, constant frequency pulse-width modulation (pwm) control scheme for excellent stability and transient response. the input voltage range of the adp2164 is 2.7 v to 6.5 v. the output voltage of the adp2164 is adjustable from 0.6 v to the input voltage (v in ). the adp2164 is also available in six preset output voltage options: 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, and 1.0 v. the adp2164 integrates a pair of low on-resistance p-channel and n-channel internal mosfets to maximize efficiency and minimize external component count. the 100% duty cycle operation allows low dropout voltage at 4 a output current. the high, 1.2 mhz pwm switching frequency allows the use of small external components, and the sync input enables multiple ics to synchronize out of phase to reduce ripple and eliminate beat frequencies. other key features of the adp2164 include undervoltage lockout (uvlo), integrated soft start to limit inrush current at startup, overvoltage protection (ovp), overcurrent protection (ocp), and thermal shutdown.
adp2164 data sheet rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? typical applications circuit ............................................................ 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? functional block diagram ............................................................ 13 ? theory of operation ...................................................................... 14 ? control scheme .......................................................................... 14 ? slope compensation .................................................................. 14 ? precision enable/shutdown ...................................................... 14 ? integrated soft start ................................................................... 14 ? oscillator and synchronization ................................................ 14 ? power good ................................................................................ 15 ? current limit and short-circuit protection ............................ 15 ? overvoltage protection (ovp) ................................................. 15 ? undervoltage lockout (uvlo) ............................................... 15 ? thermal shutdown .................................................................... 15 ? applications information .............................................................. 16 ? output voltage selection ........................................................... 16 ? inductor selection ...................................................................... 16 ? output capacitor selection ....................................................... 16 ? input capacitor selection .......................................................... 17 ? voltage tracking ......................................................................... 17 ? applications circuits ...................................................................... 18 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 19 ? revision history 12/11revision 0: initial version
data sheet adp2164 rev. 0 | page 3 of 20 specifications vin = pvin = 3.3 v, en high, sync high, t j = ?40c to +125c, unless otherwis e noted. typical values are at t j = 25c. table 1. parameter symbol test conditions/comments min typ max unit vin and pvin pins vin voltage range vin 2.7 6.5 v pvin voltage range pvin 2.7 6.5 v quiescent current i vin no switching 895 1100 a shutdown current i shdn vin = pvin = 6.5 v, en = gnd 9 12 a vin undervoltage lockout threshol d uvlo vin rising 2.6 2.7 v vin falling 2.4 2.5 v output characteristics specified by the circuit in figure 42 load regulation i o = 0 a to 4 a 0.05 %/a line regulation i o = 2 a 0.05 %/v fb pin fb regulation voltage v fb t j = ?40c to +125c 0.591 0.6 0.609 v fb bias current i fb 0.01 0.1 a sw pin high-side on resistance 1 vin = pvin = 3.3 v, i sw = 500 ma 35 52 70 m vin = pvin = 5 v, i sw = 500 ma 30 43 55 m low-side on resistance 1 vin = pvin = 3.3 v, i sw = 500 ma 24 32 40 m vin = pvin = 5 v, i sw = 500 ma 20 29 35 m sw peak current limit high-side switch, pvin = 3.3 v 5 6.2 7.4 a sw maximum duty cycle full frequency 100 % sw minimum on time 2 full frequency 100 ns trk pin trk input voltage range 0 600 mv trk to fb offset voltage trk = 0 mv to 500 mv ?15 +15 mv trk input bias current 100 na frequency switching frequency f s rt = vin 1.08 1.2 1.32 mhz rt = gnd 540 600 660 khz rt = 91 k 480 600 720 khz switching frequency range 500 1400 khz rt pin input high voltage 1.2 v rt pin input low voltage 0.45 v sync pin synchronization range 0.5 1.4 mhz minimum pulse width 100 ns minimum off time 100 ns input high voltage 1.2 v input low voltage 0.4 v pgood pin power-good range fb rising threshold 105 110 115 % fb rising hysteresis 2.5 % fb falling threshold 85 90 95 % fb falling hysteresis 2.5 % power-good deglitch time from fb to pgood 16 clock cycles power-good leakage current v pgood = 5 v 0.1 1 a power-good output low voltage i pgood = 1 ma 170 220 mv
adp2164 data sheet rev. 0 | page 4 of 20 parameter symbol test conditions/comments min typ max unit integrated soft start soft start time all switching frequencies 2048 clock cycles en pin en input rising threshold 1.12 1.2 1.28 v en input hysteresis 100 mv en pull-down resistor 1 m thermal shutdown thermal shutdown threshold t j increasing 140 c thermal shutdown hysteresis 15 c 1 pin-to-pin measurements. 2 guaranteed by design.
data sheet adp2164 rev. 0 | page 5 of 20 absolute maximum ratings table 2. parameter rating pvin, vin, sw ?0.3 v to +7 v fb, sync, trk, rt, en, pgood ?0.3 v to +7 v pgnd to gnd ?0.3 v to +0.3 v operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is measured using natural convection on a jedec 4-layer board. the exposed pad is soldered to the printed circuit board with thermal vias. table 3. thermal resistance package type ja unit 16-lead lfcsp 38.3 c/w esd caution
adp2164 data sheet rev. 0 | page 6 of 20 pin configuration and fu nction descriptions 09944-003 12 11 10 1 3 4 pvin notes 1. the exposed pad should be soldered to an external ground plane under the ic for thermal dissipation. sw sw 9 sw s ync trk 2 rt fb 6 p g n d 5 g n d 7 p g n d 8 p g n d 1 6 p g o o d 1 5 e n 1 4 v i n 1 3 p v i n adp2164 top view (not to scale) figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 sync synchronization input. to synchronize the switching frequency to an external clock, connect this pin to an external clock with a frequency of 500 khz to 1.4 mhz (see the oscillator and synchronization section for more information). 2 rt frequency setting. to select a switching frequency of 600 khz, connect this pin to gnd; to select a switching frequency of 1.2 mhz, connect this pin to vin. to program the frequency from 500 khz to 1.4 mhz, connect a resistor from this pin to gnd (see the oscillator and synchronization section for more information). 3 trk tracking input. to track a master voltage, connect the trk pin to a voltage divider from the master voltage. if the tracking function is not used, connect the trk pin to vin. for more information, see the voltage tracking section. 4 fb feedback voltage sense input. connect this pin to a resistor divider from v out . for the preset output version, connect this pin directly to v out . 5 gnd analog ground. connect to the ground plane. 6, 7, 8 pgnd power ground. connect to the ground plane and to the output return side of the output capacitor. 9, 10, 11 sw switch node output. connect to the output inductor. 12, 13 pvin power input pin. connect this pin to the input power source. connect a bypass capacitor between this pin and pgnd. 14 vin bias voltage input pin. connect a bypass capacitor between this pin and gnd; connect a small (10 ) resistor between this pin and pvin. 15 en precision enable pin. the external resistor divider can be used to set the turn-on threshold. to enable the part automatically, connect the en pin to vin. this pin has a 1 m pull-down resistor to gnd. 16 pgood power-good output (open drain). connect this pin to a resistor from any pull-up voltage lower than 6.5 v. 17 (epad) exposed pad the exposed pad should be soldered to an external ground plane under the ic for thermal dissipation.
data sheet adp2164 rev. 0 | page 7 of 20 4 typical performance characteristics t j = 25c, v in = 5 v, v out = 1.2 v, l = 1 h, c in = 47 f, c out = 100 f, unless otherwise noted. 100 90 80 70 60 50 40 30 01 23 output current (a) efficiency (%) 09944-004 inductor: coilcraft mss1038-152nlb v out = 0.6v v out = 1.0v v out = 1.2v v out = 1.8v v out = 2.5v figure 4. efficiency vs. output current, v in = 3.3 v, f s = 600 khz 100 90 80 70 60 50 40 30 01 23 output current (a) efficiency (%) 09944-005 4 inductor: coilcraft mss1038-102nlb v out = 0.6v v out = 1.0v v out = 1.2v v out = 1.8v v out = 2.5v figure 5. efficiency vs. output current, v in = 3.3 v, f s = 1.2 mhz 1050 1000 950 900 850 800 750 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 v in (v) quiescent current (a) 09944-006 t j = ?40c t j = +25c t j = +125c figure 6. quiescent current vs. v in (no switching) 100 90 80 70 60 50 40 30 01 23 output current (a) efficiency ( 4 % ) 09944-007 inductor: coilcraft mss1038-152nlb v out =0.6v v out =1.0v v out =1.2v v out =1.8v v out =2.5v v out =3.3v figure 7. efficiency vs. output current, v in = 5 v, f s = 600 khz 100 90 80 70 60 50 40 30 01 23 output current (a) efficiency (%) 09944-008 4 inductor: coilcraft mss1038-102nlb v out = 1.0v v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v figure 8. efficiency vs. output current, v in = 5 v, f s = 1.2 mhz 11 10 9 8 7 6 5 4 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 v in (v) shutdown current (a) 09944-009 t j = ?40c t j = +25c t j = +125c figure 9. shutdown current vs. v in
adp2164 data sheet rev. 0 | page 8 of 20 606 605 604 603 602 601 600 599 598 597 596 595 594 ?40 ?20 0 20 40 60 80 100 120 temperature (c) feedback voltage (mv) 09944-010 figure 10. feedback voltage vs. temperature, v in = 3.3 v 80 70 60 50 40 30 20 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 v in (v) pfet resistor (m ? ) 09944-011 t j = ?40c t j = +25c t j = +125c figure 11. pfet resistor vs. v in (pin-to-pin measurements) 1300 1275 1250 1225 1200 1175 1100 1150 1125 frequency (khz) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 v in (v) 09944-012 t j = ?40c t j = +25c t j = +125c figure 12. switching frequency vs. v in , f s = 1.2 mhz (rt = vin) 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 ?40 ?20 0 20 40 60 80 100 120 temperature (c) enable threshold (v) 09944-013 rising falling figure 13. en threshold vs. temperature 60 50 40 30 20 10 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 v in (v) nfet resistor (m ? ) 09944-014 t j = ?40c t j = +25c t j = +125c figure 14. nfet resistor vs. v in (pin-to-pin measurements) 650 640 630 620 610 600 590 580 550 570 560 frequency (khz) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 v in (v) 09944-015 t j = ?40c t j = +25c t j = +125c figure 15. switching frequency vs. v in , f s = 600 khz (rt = gnd)
data sheet adp2164 rev. 0 | page 9 of 20 650 640 630 620 610 600 590 580 570 560 550 frequency (khz) 09944-016 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 v in (v) t j = ?40c t j = +25c t j = +125c figure 16. switching frequency vs. v in , f s = 600 khz (rt = 91 k) 6.8 6.6 6.4 6.2 6.0 5.8 5.6 5.4 5.2 ?40 ?20 0 20 40 60 80 100 120 temperature (c) peak current limit (a) 09944-017 figure 17. peak current limit vs. temperature, v in = 3.3 v 09944-018 ch1 500mv ch2 5.00v ch3 5.00v ch4 2.00a ? m 1.00ms a ch3 2.50v 1 3 4 2 t 20.20% t en pgood i l v out figure 18. soft start with full load, v in = 5 v, v out = 1.2 v, f s = 1.2 mhz 2.70 2.68 2.66 2.64 2.62 2.60 2.58 2.56 2.54 2.52 2.50 2.48 2.46 2.44 2.42 2.40 ?40 ?20 0 20 40 60 80 100 120 temperature (c) uvlo threshold (v) 09944-019 rising falling figure 19. uvlo threshold vs. temperature, v in = 3.3 v 7.0 6.8 6.6 6.4 6.2 6.0 5.8 5.6 5.4 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 6.3 v in (v) 09944-020 peak current limit (a) figure 20. peak current limit vs. v in , t j = 25c 09944-021 ch1 500mv ch2 5.00v ch3 5.00v ch4 2.00a ? m 1.00ms a ch3 2.50v 1 3 4 2 t 20.20% t en pgood i l v out figure 21. soft start with precharged output voltage, v in = 5 v, f s = 1.2 mhz
adp2164 data sheet rev. 0 | page 10 of 20 i o 09944-022 ch1 100mv ch4 2.00a ? m 200s a ch4 2.52a 4 1 t 20.20% t b w v out (ac) figure 22. load transient, 0.5 a to 3.5 a load step, v in = 5 v, v out = 1.2 v, f s = 1.2 mhz 09944-023 ch1 5.00v ch2 2.00v m 400ns a ch1 2.50v 1 2 t 60.40% t sw sync figure 23. adp2164 synchronized to 1 mhz, in phase 09944-024 ch1 500mv ch2 5.00v ch4 5.00a ? m 2.00ms a ch1 680mv 2 4 1 t 30.20% t sw v out i l b w b w figure 24. output short i o 09944-025 ch1 100mv ch4 2.00a ? m 200s a ch4 2.52a 4 1 t 20.20% b w t v out (ac) figure 25. load transient, 0.5 a to 3.5 a load step, v in = 5 v, v out = 1.2 v, f s = 600 khz 09944-026 ch1 5.00v ch2 2.00v m 400ns a ch1 2.50v 1 2 t 60.40% sw t sync figure 26. adp2164 synchronized to 1 mhz, 180 out of phase 09944-027 ch1 500mv ch2 5.00v ch4 5.00 a ? m 2.00ms a ch1 680mv 2 4 1 t 60.60% t sw v out i l b w b w figure 27. output short recovery
data sheet adp2164 rev. 0 | page 11 of 20 09944-028 ch2 500mv ch4 500mv m 2.00ms a ch2 820mv 4 t 40.40% t trk fb b w b w figure 28. tracking function 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 1k 10k 12 100k 1m frequency (hz) magnitude (db) phase (degrees) 09944-029 cross frequency: 57khz phase margin: 67 phase magnitude figure 29. bode plot at v in = 5 v, v out = 1.0 v, i o = 4 a, f s = 1.2 mhz, l = 0.68 h, c out = 2 100 f 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 1k 10k 12 100k 1m frequency (hz) magnitude (db) phase (degrees) 09944-030 cross frequency: 52khz phase margin: 69 phase magnitude figure 30. bode plot at v in = 5 v, v out = 1.5 v, i o = 4 a, f s = 1.2 mhz, l = 1 h, c out = 47 f + 100 f 09944-031 ch1 5.00mv ch2 5.00v ch4 2.00a ? m 400ns a ch2 3.30v 2 1 4 t 30.60% t sw v out i l figure 31. steady waveform, v in = 5 v, v out = 1.2 v, f s = 1.2 mhz 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 1k 10k 1 2 100k 1m frequency (hz) magnitude (db) phase (degrees) 09944-032 cross frequency: 61khz phase margin: 69 phase magnitude figure 32. bode plot at v in = 5 v, v out = 1.2 v, i o = 4 a, f s = 1.2 mhz, l = 0.68 h, c out = 47 f + 100 f 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 1k 10k 12 100k 1m frequency (hz) magnitude (db) phase (degrees) 09944-033 cross frequency: 61khz phase margin: 66 phase magnitude figure 33. bode plot at v in = 5 v, v out = 1.8 v, i o = 4 a, f s = 1.2 mhz, l = 1 h, c out = 100 f
adp2164 data sheet rev. 0 | page 12 of 20 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 1k 10k 12 100k 1m frequency (hz) magnitude (db) phase (degrees) 09944-034 cross frequency: 83khz phase margin: 60 phase magnitude figure 34. bode plot at v in = 5 v, v out = 2.5 v, i o = 4 a, f s = 1.2 mhz, l = 1 h, c out = 47 f 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 1k 10k 12 100k 1m frequency (hz) magnitude (db) phase (degrees) 09944-035 cross frequency: 68khz phase margin: 65 phase magnitude figure 35. bode plot at v in = 5 v, v out = 3.3 v, i o = 4 a, f s = 1.2 mhz, l = 1 h, c out = 47 f
data sheet adp2164 rev. 0 | page 13 of 20 functional block diagram 09944-036 soft start + + + ? g m z comp error amp logic control 0.6v pfet nfet 0.66v 0.54v + ? + ? pmos current sense amp nmos current sense amp oscillator slope compensation regulator uvlo adp2164 pgnd clk rt sync v in en pvin sw gnd pgood fb trk figure 36. functional block diagram
adp2164 data sheet rev. 0 | page 14 of 20 theory of operation integrated soft start the adp2164 is a step-down dc-to-dc regulator that uses a fixed-frequency, peak current mode architecture with an integrated high-side switch and low-side synchronous rectifier. the high switching frequency and tiny, 16-lead, 4 mm 4 mm lfcsp package provide a small, step-down dc-to-dc regulator solution. the integrated high-side switch (p-channel mosfet) and synchronous rectifier (n-channel mosfet) yield high efficiency. the adp2164 has integrated soft start circuitry to limit the output voltage rise time and reduce inrush current at startup. the soft start time is set at 2048 clock cycles. if the output voltage is precharged before the part is turned on, the adp2164 prevents a reverse inductor currentwhich would discharge the output capacitoruntil the soft start voltage exceeds the voltage on the fb pin. the adp2164 operates with an input voltage from 2.7 v to 6.5 v and regulates the output voltage down to 0.6 v. the adp2164 is also available with preset output voltage options of 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, and 1.0 v. oscillator and synchronization the adp2164 switching frequency is controlled by the rt pin. if the rt pin is connected to gnd, the switching frequency is set to 600 khz. if the rt pin is connected to vin, the switching frequency is set to 1.2 mhz. control scheme the adp2164 uses a fixed-frequency, peak current mode pwm control architecture. at the start of each oscillator cycle, the p-channel mosfet switch is turned on, placing a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current level, turns off the p-channel mosfet switch, and turns on the n-channel mosfet synchronous rectifier. this action places a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle. connecting a resistor from rt to gnd allows programming of the switching frequency from 500 khz to 1.4 mhz. use the following equation to set the switching frequency: (khz) 000,54 )(k s f rt = figure 37 shows the typical relationship between the switching frequency and the rt resistor. 1600 1400 1200 1000 800 600 400 200 20 40 60 80 100 120 140 160 180 rt resistor (k ? ) frequency (khz) 09944-037 the peak inductor current level is set by the compensation (comp) voltage. the comp voltage is the output of a transcon- ductance error amplifier that compares the feedback voltage with an internal 0.6 v reference (see figure 36 ). slope compensation to prevent subharmonic oscillations, slope compensation stabilizes the internal current control loop of the adp2164 when the part operates at or beyond a 50% duty cycle. slope compensation is implemented by summing an artificial voltage ramp with the current sense signal during the on time of the p-channel mosfet switch. this voltage ramp depends on the output voltage. when operating at high output voltages, slope compensation increases. the slope compensation ramp value determines the minimum inductor value that can be used to prevent subharmonic oscillations. figure 37. switching frequency vs. rt resistor to synchronize the adp2164 , drive an external clock at the sync pin. the frequency of the external clock can be in the range of 500 khz to 1.4 mhz. precision enable/shutdown the en pin is a precision analog input that enables the device when the voltage exceeds 1.2 v (typical); this pin has 100 mv hysteresis. when the enable voltage falls below 1.1 v (typical), the part turns off. to force the adp2164 to start automatically when input power is applied, connect the en pin to the vin pin. when the sync pin is driven by an external clock, the user can configure the switching frequency to be in phase with the external clock or 180 out of phase with the external clock, as follows: ? if the rt pin is connected to gnd or to a resistor, the switching frequency is in phase with the external clock. when the adp2164 is shut down, the soft start capacitor is discharged. this causes a new soft start cycle to begin when the part is reenabled. ? if the rt pin is connected to vin, the switching frequency is 180 out of phase with the external clock. an internal pull-down resistor (1 m) prevents accidental enabling of the part if the en input is left floating.
data sheet adp2164 rev. 0 | page 15 of 20 power good pgood is an active high, open-drain output and requires a resistor to pull it up to the logic supply voltage. pgood high indicates that the voltage on the fb pin (and, therefore, the output voltage) is within 10% of the desired value. pgood low indicates the opposite. there is a 16-cycle waiting period after the fb voltage is detected as being out of bounds. if fb returns to within the 10% range, it is ignored by the pgood circuitry. current limit and short-circuit protection the adp2164 has a peak current limit protection circuit to prevent current runaway. the peak current limit is 6.2 a. when the inductor current reaches the peak current limit, the high-side mosfet turns off and the low-side mosfet turns on until the next cycle begins. the overcurrent counter is incremented by 1 at each peak current limit event. if the overcurrent counter exceeds 10, the part enters hiccup mode, and the high-side fet and low-side fet are both turned off. the part remains in this mode for 4096 clock cycles and then attempts to restart using soft start. if the current limit fault has cleared, the part resumes normal operation. if the current limit fault has not cleared, the part reenters hiccup mode after first counting 10 current limit violations. overvoltage protection (ovp) overvoltage protection (ovp) circuitry is integrated in the adp2164 . the output voltage is continuously monitored by a comparator through the fb pin, which is at 0.6 v (typical) under normal operation. the comparator is activated when the fb voltage exceeds 0.66 v (typical ), thus indicating an output overvoltage condition. if the voltage remains above the ovp threshold for 16 clock cycles, the high-side mosfet turns off and the low-side mosfet turns on until the current through it reaches the ?1.3 a current limit. both mosfets remain in the off state until fb falls below 0.54 v (typical), after which the part restarts. the behavior of pgood under this condition is described in the power good section. undervoltage lockout (uvlo) undervoltage lockout (uvlo) circuitry is integrated in the adp2164 . if the input voltage falls below 2.5 v, the adp2164 shuts down, and both the power switch and the synchronous rectifier turn off. when the voltage rises above 2.6 v again, the soft start is initiated, and the part is enabled. thermal shutdown if the adp2164 junction temperature rises above 140c, the thermal shutdown circuit turns off the regulator. extreme junc- tion temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. when thermal shutdown occurs, a 15c hysteresis ensures that the adp2164 does not return to operation until the on-chip temperature falls below 125c. soft start is initiated when the part comes out of thermal shutdown.
adp2164 data sheet rev. 0 | page 16 of 20 applications information the typical application circuit for the adp2164 is shown in figure 38 . 09944-042 adp2164acpz c in 47f x5r 10v c out1 47f x5r 6.3v c out2 100f x5r 6.3v v out 1.2v 4a v in 3.3v sync trk fb rt sw sw sw pvin gnd pgnd pgnd pgnd l 0.8h r top 10k ? r bot 10k ? l: mss1048-801nl coilcraft c in : c3225x5r1a476m tdk c out1 : c3225x5r0j476m tdk c out2 : c3225x5r0j107m tdk 12 11 10 9 4 3 2 1 5678 pgood c1 0.1f en r1 10? r2 10k ? pvin 16 15 vin 14 13 figure 38. typical application circuit output voltage selection the output voltage of the adjustable version of the adp2164 is set by an external resistive voltage divider using the following equation: u bot top out r r v 16.0 to limit output voltage accuracy degradation due to fb bias current (0.1 a maximum) to less than 0.5% (maximum), ensure that r bot is less than 30 k. inductor selection the inductor value is determined by the operating frequency, input voltage, output voltage, and ripple current. a small inductor value provides larger inductor current ripple and fast transient response but degrades efficiency; a large inductor value provides small inductor current ripple and good efficiency but slows transient response. for a reasonable trade-off between transient response and efficiency, the inductor current ripple, i l , is typically set to one-third the maximum load current. the inductor value is calculated using the following equation: s l out in fi dvv l u u where: v in is the input voltage. v out is the output voltage. i l is the inductor current ripple. f s is the switching frequency. d is the duty cycle (v out /v in ). the adp2164 uses slope compensation in the current control loop to prevent subharmonic oscillations when the duty cycle is larger than 50%. the internal slope compensation limits the minimum inductor value. the negative current limit (?1.3 a) also limits the minimum inductor value. the inductor current ripple (i l ) calculated by the selected inductor should not exceed 2.6 a. the peak inductor current should be kept below the peak current limit threshold and is calculated using the following equation: 2 l o peak i ii ensure that the rms current of the selected inductor is greater than the maximum load current and that its saturation current is greater than the peak current limit of the converter. output capacitor selection the output capacitor value is determined by the output voltage ripple, load step transient, and loop stability. the output ripple is determined by the esr and the capacitance. uu u s out l out fc esriv 8 1 the load step transient response depends on the inductor, the output capacitor, and the current control loop. the adp2164 has integrated loop compensation for simple power design. table 5 and table 6 show the recommended values for inductors and capacitors for the adp2164 based on the input and output voltages for the part. x5r or x7r dielectric ceramic capacitors are highly recommended. table 5. recommended l and c out values at f s = 1.2 mhz v in (v) v out (v) l (h ) c out (f) 3.3 1.0 0.8 100 + 100 3.3 1.2 0.8 100 + 47 3.3 1.5 1 100 + 47 3.3 1.8 1 100 3.3 2.5 1 47 5 1.0 0.8 100 + 100 5 1.2 0.8 100 + 47 5 1.5 1 100 + 47 5 1.8 1 100 5 2.5 1 47 5 3.3 1 47
data sheet adp2164 rev. 0 | page 17 of 20 table 6. recommended l and c out values at f s = 600 khz v in (v) v out (v) l (h ) c out (f) 3.3 1.0 1 100 + 100 3.3 1.2 1 100 + 100 3.3 1.5 1 100 + 47 3.3 1.8 1 100 + 47 3.3 2.5 1 100 5 1.0 1 100 + 100 5 1.2 1.5 100 + 100 5 1.5 1.5 100 + 47 5 1.8 1.5 100 + 47 5 2.5 1.5 100 5 3.3 1.5 100 higher or lower values of inductors and output capacitors can be used in the regulator, but system stability and load transient performance must be verified. table 7 and table 8 list some recommended inductors and capacitors for the adp2164 . table 7. recommended inductors manufacturer part no. coilcraft? mss1038, mss1048, mss1260 sumida cdrh103r, cdrh104r, cdrh105r table 8. recommended capacitors manufacturer part no. description murata GRM32ER60J107ME20 100 f, 6.3 v, x5r, 1210 murata grm32er60j476me20 47 f, 6.3 v, x5r, 1210 tdk c3225x5r0j107m 100 f, 6.3 v, x5r, 1210 tdk c3225x5r0j476m 47 f, 6.3 v, x5r, 1210 input capacitor selection the input capacitor reduces the input voltage ripple caused by the switch current on pvin. place the input capacitor as close as possible to the pvin pins. a 22 f or 47 f ceramic capacitor is recommended. the rms current rating of the input capacitor should be larger than the value calculated using the following equation: () ?= 1 where d is the duty cycle. voltage tracking the adp2164 includes a tracking feature that allows the adp2164 output (slave voltage) to be configured to track an external voltage (master voltage), as shown in figure 39 . v adp2164 r top r bot r trkt r trkb v slave master trk fb 09944-039 figure 39. voltage tracking coincident tracking a common requirement is coincident tracking, as shown in figure 40 . coincident tracking limits the slave output voltage to the same value as the master voltage until the slave output voltage reaches regulation. connect the trk pin to a resistor divider driven from the master voltage, as shown in figure 39 . for coincident tracking, set r trkt = r top and r trkb = r bot . oltage time v slave v master v 09944-040 figure 40. coincident tracking ratiometric tracking ratiometric tracking is shown in figure 41 . the slave output is limited to a fraction of the master voltage. in this application, the slave and master voltages reach their final values at the same time. oltage time v slave v master v 09944-041 figure 41. ratiometric tracking the ratio of the slave output voltage to the master voltage is a function of the two dividers. trkb trkt bot top master slave r r r v v + + = 1 1 r
adp2164 data sheet rev. 0 | page 18 of 20 applications circuits 09944-042 adp2164acpz c in 47f x5r 10v c out1 47f x5r 6.3v c out2 100f x5r 6.3v v out 1.2v 4a v in 3.3v sync trk fb rt sw sw sw pvin gnd pgnd pgnd pgnd l 0.8h r top 10k ? r bot 10k? l: mss1048-801nl coilcraft c in : c3225x5r1a476m tdk c out1 : c3225x5r0j476m tdk c out2 : c3225x5r0j107m tdk 12 11 10 9 4 3 2 1 5678 pgood c1 0.1f en r1 10? r2 10k? pvin 16 15 vin 14 13 figure 42. 1.2 v, 4 a, 1.2 mhz step-down regulator 09944-044 adp2164acpz c in 47f x5r 10v c out 100f x5r 6.3v v out 1.8v 4a v in 5v sync trk fb rt sw sw sw pvin gnd pgnd pgnd pgnd l 1h 1mhz ext clock r top 20k ? r bot 10k ? 12 11 10 9 4 3 2 1 5678 pgood c1 0.1f en r1 10? r2 10k? pvin 16 15 vin 14 13 l: mss1038-102nl coilcraft c in : c3225x5r1a476m tdk c out : c3225x5r0j107m tdk figure 43. 1.8 v, 4 a step-down regulator, synchronized to 1 mhz, in phase with the external clock 09944-046 adp2164acpz-1.2 c in 47f x5r 10v v out 1.2v 4a v in 5v sync trk fb rt sw sw sw pvin gnd pgnd pgnd pgnd l 0.8h l: mss1048-801nl coilcraft c in : c3225x5r1a476m tdk c out1 : c3225x5r0j476m tdk c out2 : c3225x5r0j107m tdk 12 11 10 9 4 3 2 1 5678 pgood c1 0.1f en r1 10? r2 10k ? pvin 16 15 vin 14 13 c out1 47f x5r 6.3v c out2 100f x5r 6.3v figure 44. fixed 1.2 v, 4 a, 1.2 mhz step-down regulator 09944-043 adp2164acpz c in 47f x5r 10v c out 47f x5r 6.3v v out 3.3v 4a v in 5v sync trk fb rt sw sw sw pvin gnd pgnd pgnd pgnd l 1h r t 54k? r top 10k ? r bot 2.21k ? l: mss1038-102nl coilcraft c in : c3225x5r1a476m tdk c out : c3225x5r0j476m tdk 12 11 10 9 4 3 2 1 5678 pgood c1 0.1f en r1 10 ? r2 10k? pvin 16 15 vin 14 13 figure 45. 3.3 v, 4 a, 1 mhz step-down regulator 09944-045 adp2164acpz c in 47f x5r 10v v out 1.5v 4a v in 5v sync trk fb rt sw sw sw pvin gnd pgnd pgnd pgnd l 1h 1mhz ext clock r top 15k ? r bot 10k ? l: mss1038-102nl coilcraft c in : c3225x5r1a476m tdk c out1 : c3225x5r0j476m tdk c out2 : c3225x5r0j107m tdk 12 11 10 9 4 3 2 1 5678 pgood c1 0.1f en r1 10? r2 10k? pvin 16 15 vin 14 13 c out1 47f x5r 6.3v c out2 100f x5r 6.3v figure 46. 1.5 v, 4 a step-down regulator, synchronized to 1 mhz, 180 out of phase with the external clock 09944-047 adp2164acpz c in 47f x5r 10v c out 47f x5r 6.3v v out 3.3v 4a v in 5v sync trk fb rt sw sw sw pvin gnd pgnd pgnd pgnd l 1h r top 10k ? r bot 2.21k ? r trkb 2.21k ? r trkt 10k ? v master l: mss1038-102nl coilcraft c in : c3225x5r1a476m tdk c out : c3225x5r0j476m tdk 12 11 10 9 4 3 2 1 5678 pgood c1 0.1f en r1 10 ? r2 10k ? pvin 16 15 vin 14 13 figure 47. 3.3 v, 4 a, 1.2 mhz step-down regulator, tracking mode
data sheet adp2164 rev. 0 | page 19 of 20 outline dimensions compliant to jedec standards mo-220-wggc. 042709-a 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.50 0.40 0.30 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 2.60 2.50 sq 2.40 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 48. 16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-16-26) dimensions shown in millimeters ordering guide model 1 temperature range output voltage pa ckage description package option adp2164acpz-r7 ?40c to +125c adjustable 16-lead lfcsp_wq cp-16-26 adp2164acpz-1.0-r7 ?40c to +125c 1.0 v 16-lead lfcsp_wq cp-16-26 adp2164acpz-1.2-r7 ?40c to +125c 1.2 v 16-lead lfcsp_wq cp-16-26 adp2164acpz-1.5-r7 ?40c to +125c 1.5 v 16-lead lfcsp_wq cp-16-26 adp2164acpz-1.8-r7 ?40c to +125c 1.8 v 16-lead lfcsp_wq cp-16-26 adp2164acpz-2.5-r7 ?40c to +125c 2.5 v 16-lead lfcsp_wq cp-16-26 adp2164acpz-3.3-r7 ?40c to +125c 3.3 v 16-lead lfcsp_wq cp-16-26 adp2164-evalz evaluation board 1 z = rohs compliant part.
adp2164 data sheet rev. 0 | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09944-0-12/11(0)

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